The present invention relates generally to amplifier circuits, and more particularly to improving amplifier performance by overcoming difficulties caused by capacitance associated with the bulk electrodes of the input field effect transistors.
Bulk electrode capacitance associated with input stages of high-speed operational amplifiers reduces the amplifier slew rates and also causes unsymmetrical operational amplifier responses to the positive-going and negative-going edges of large-magnitude input step signals. Prior Art FIG. 1 illustrates an operational amplifier including a differential input transconductance stage 2 including input transistors 6A and 6B having their sources connected by conductor 8 to a tail current source 7. The bulk electrodes of input transistors 6A and 6B are connected by conductor 10 to the positive supply voltage VDD. The drains of input transistors 6A and 6B are connected to inputs of a prior art folded cascode stage 3, the outputs of which are connected to the inputs of a conventional class AB stage 4.
In the circuit of Prior Art FIG. 1, the bulk electrode capacitance Cb of the bulk electrodes of the input transistors does not significantly affect the signal path of the input signal (Vin=Vin+−Vin−) through the operational amplifier. However, the CMRR (common mode rejection ratio) of the operational amplifier is degraded due to mismatching between input transistors 6A and 6B, since the CMRR is a function of the source-drain voltages of the input transistors 6A and 6B.
Prior Art FIG. 2 shows another configuration of a similar transconductance input stage 2A in which the bulk electrodes of its of input transistors 6A and 6B are connected by conductor 10A to the common source conductor 8, rather than to VDD as in FIG. 1. A cascode transistor 11A is coupled between the drain of input transistor 6A and output conductor 9A, with its gate also connected to Vin−, and a cascode transistor 11B is coupled between the drain of input transistor 6B and output conductor 9B, with its gate connected to Vin+. Cascode transistors 11A and 11B provide improved CMRR of the operational amplifier by providing a relatively constant drain-source voltage across input transistors 6A and 6B. However, the circuit configuration of Prior Art FIG. 2 causes the bulk electrode capacitance Cb to be coupled so as to directly load the amplifier signal path, thereby degrading the large signal response of the amplifier by causing slower settling times and unsymmetrical slew rates.
Specifically, if the bulk electrodes of the input transistors are connected directly to their sources as shown in FIG. 2, the total bulk electrode capacitance Cb can be considered to be added directly to the signal path capacitance. This causes the above-mentioned unsymmetrical slewing operation wherein the rising edge of Vout is slower than the falling edge. For most operational amplifiers, the slew rate is determined by the total input stage tail current divided by the Miller compensation capacitance CM. If all of the input stage tail current flows to the Miller compensation capacitance CM, it does not matter whether that occurs in response to a rising edge or falling edge of the operational amplifier step input pulse. However, if the bulk electrode capacitance Cb of the input transistors 6A and 6B is connected directly to their sources, the total increased capacitance associated with the bulk electrodes of the input transistors 6A and 6B must be charged or discharged during slewing operation and therefore causes slower slewing rates.
During the rising edge of the amplifier input voltage, some of the tail current will go to the source capacitance of input transistors 6A and 6B, so less of the tail current is available to charge the Miller compensation capacitance CM of the operational amplifier output stage 4, resulting in a decreased slew rate.
During the falling edge of the input step pulse, the voltage of the common source conductor 8 of input transistors 6A and 6B will decrease. The total capacitance on common source conductor 8, including source capacitances of input transistors 6A and 6B and the total bulk electrode capacitance Cb, will be discharged through input transistors 6A and 6B and conductors 9A and 9B and through the signal path of the folded cascode stage 3 to the Miller compensation capacitances CM and will produce a current that is substantially greater in magnitude than the tail current I1 of input stage 2A. This causes a substantially faster slew rate than for the rising edge of the input step voltage pulse. Thus, the slewing rates in response to the rising and falling edges of a step voltage input pulse are unsymmetrical.
Conventional buffer circuits may have been previously used to drive the bulk electrodes of operational amplifier input stage field effect transistors, but if so, it would have been found that this approach has significant difficulties because some of the tail current of the conventional buffer circuit would have been leaked to the integrated circuit substrate or ground, i.e., wasted, and therefore resulting in less of the tail current being available to drive the bulk electrode capacitance Cb. This would have resulted in excessive power consumption if the tail current had been substantially increased to drive the bulk electrode capacitance in order to increase output slew rates.
Thus, there is an unmet need for an amplifier input stage that provides symmetrical slew rates.
There also is an unmet need for an amplifier input stage that provides symmetrical slew rates and fast signal settling times.
There also is an unmet need for an amplifier input stage that provides symmetrical slew rates and fast signal settling times without unacceptably increasing power consumption.